Note too that the "stop" to data acquisition is effectively up to the PC (through its polling with command 50), and all of the latency that involves. it is hence quite possible that the FX2 FIFO will be reloaded with additional data before a true stop. The only trouble is that the firmware resets the FX2 FIFO before it stop and resets the CPLD (and its FIFO). I note that the 50 command not only checks the status of the CPLD fifo, but also stops data acquisition by the CPLD (if the device has marked its FIFO as full). EDIT In starting to work out how to generate and receive an external trigger, I have looked closely at the DDS140 firmware. I think both Doctormord and I are keen on decent data logging capabilities. are we convinced that after the initial bad data, the scopes give data streams without dropouts (obviously excluding the DDS140 when it is in flash, ie normal, mode). oh and of course continuous data capture. Once I have considered carefully how to implement a hardware trigger, that is next on my list. I am leaving this one to you guys (as the experts). I have observed the same behaviour on one channel, but one only. Yes, your observation on Jimons clipped channel. Perhaps even limited differences in gain between the two channels could cause the observed shift. His LTspice simulation shows that phase is all over the place up at the top end frequencies. Doctormord did a good job of tracing the front end here and here. Do you see problems with that? mmark, I agree that there is a phase shift, but I am not sure I see 180 degrees on Jimons post. I am proposing to buffer INT5 with an opto, collector tied to +3v with a 10k resistor. have you taken that subject further since you mentioned your concerns? And a quick question. Now that I have (software) corrected these I need to look at gain nonlinearities. Significant 0v offsets and appalling gain variability. Having a tuned circuit to adjust costs money! BTW, Doctormord, I have done some calibration of the analogue front end. The only thing I would note is that for the designers of these scopes, wouldnt it have been easier to use antiphase clocks to the ADC. Doctormord and Ganzuul are certainly more hardware capable than me. I have not looked at the analogue front end too much. However Ganzuuls observation is an interesting one. Well Doctormord is right about the ADC, the DDS120 and DDS140 (without modification) will do no phase shifting between their two inputs.
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